1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an elevated source/drain MOSFET structure in the fabrication of integrated circuits.
2. Description of the Prior Art
Conventional MOS transistors have gates that are of a greater height than the source/drain regions. Hence, during the subsequent contact opening step, the gate suffers from excessive plasma induced damage (PID) because the etching of the pre-metal dielectric will first be completed at the gate before the source/drain regions are exposed. Furthermore, during formation of salicides on the source/drain regions, there is a tendency for the junction to be consumed as junction depths decrease to less than about 100 nanometers. It is desired to solve the dual problems of PID and junction consumption.
A number of workers in the art have proposed elevated source/drain structures. U.S. Pat. No. 6,133,106 to Evans et al discloses source/drain regions and gate of the same height where the gate is formed by a dummy gate replacement method. U.S. Pat. No. 6,271,132 to Xiang et al shows contact regions over the source/drain regions where the contact regions have the same height as the gate. U.S. Pat. No. 5,571,738 teaches short channel FET""s with polysilicon source/drains shorter than the gate. U.S. Pat. No. 6,225,173 to Yu and U.S. Pat. No. 6,090,672 to Wanless show damascene gate processes.
A principal object of the present invention is to provide an effective and very manufacturable method of forming a MOSFET having elevated source/drain structures.
A further object of the invention is to provide a method of forming a MOSFET having an elevated source/drain structure having the same height as the height of the gate electrode.
Yet another object is to provide a method of forming a MOSFET having an elevated source/drain structure having the same height as the height of the gate electrode wherein plasma induced damage to the gate is reduced.
A further object is to provide a method of forming a MOSFET having an elevated source/drain structure having the same height as the height of the gate electrode wherein junction consumption during silicidation is eliminated.
A still further object is to provide a method of forming a MOSFET having an elevated source/drain structure having the same height as the height of the gate electrode wherein plasma induced damage to the gate is reduced and junction consumption during silicidation is eliminated.
In accordance with the objects of this invention a method for forming a MOSFET having an elevated source/drain structure is achieved. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening. The gate material layer, first polysilicon spacers and second polysilicon spacers are polished back to the polish stop layer thereby completing formation of a MOSFET having an elevated source/drain structure in the fabrication of an integrated circuit device.